A computing system may require high levels of reliability, availability and serviceability (RAS) features. In many cases, RAS-related operations may require changes to the system configuration such as, for example, adding memory, removing memory, adding a processor, and removing a processor. Some known computing systems may provide an interrupt mechanism that enables the OS to be put into a quiescent state so that certain RAS features can be implemented in an OS transparent manner. Normally, due to real-time demands, the OS may impose latency limitations for the interrupt mechanism.